Sharp VL-A10K Technické informace Strana 55

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Analog Input
VSBC-6 Reference Manual Reference43
ADC D
ATA
H
IGH
R
EGISTER
ADCHI (READ) 00E5h (or 01E5h via CMOS Setup)
D7 D6 D5 D4 D3 D2 D1 D0
D11 / 0 D11 / 0 D11 / 0 D11 / 0 D11 D10 D9 D8
The ADCHI register is a read register containing the upper 4 bits of data from the A/D
conversion results. It is used in conjunction with the ADCLO register to read the complete 12-bit
data word.
When reading data, it is normal convention to read the ADCLO register first, followed by the
ADCHI register.
Table 20: ADCHI Bit Assignments
Bit Mnemonic Description
D7-D4 D11 / 0
Sign Extension
— These four bits read as "0" in unipolar input mode
(BIP = 0), in bipolar input mode, D11 is duplicated (sign extended) into
these four bits.
D3-D0 ADCDATA A/D Input Data (Most Significant Nibble) — These bits contain data
bits D11 through D8 of the conversion results.
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